Digital electronic systems are commonly implemented by combining and interconnecting several different integrated circuit (IC) devices such as processors, memory devices and programmable logic devices. The various IC devices communicate with one another by way of input and output (I/O) signals transmitted over a system bus, and several different I/O standards exist for this purpose. One prevalent I/O standard is Low Voltage Differential Signaling (LVDS). LVDS is a low noise, low power, and high-speed I/O interface that uses differential signals without a reference voltage and therefore requires two signal lines for each signal channel. The voltage difference between the two signal lines defines the logic state of the LVDS signal.
Generally, an LVDS output driver in a transmitting device converts a single-ended digital logic signal—e.g., a CMOS (Complementary Metal Oxide Semiconductor) or TTL (Transistor-Transistor Logic) logic level signal—into the LVDS differential format. The differential signal generated by an LVDS output driver has a typical voltage swing of about 350 mV and a typical common-mode voltage of about 1.2 V on the two LVDS signal lines. The small voltage swing in the LVDS signal makes the standard well-suited for high-speed data transmission. From the output driver, the LVDS signals are transmitted to another device having an LVDS receiver for converting the differential signal back into a desired single-ended logic signal format. The LVDS receiver includes an input buffer circuit powered by an I/O supply voltage VCC. The VCC I/O supply typically equals 3.3 V, however the voltage swing in the LVDS standard is not dependent on power supply levels. Generally, the LVDS receiver must be able to tolerate a ±1 V shift between the ground reference of the output driver and the receiver ground. Therefore, where the LVDS signal provided by an output driver swings from 1.0-1.4 V, the LVDS input buffer must be able to operate properly with input voltage swings that range from 0.0-0.4 V in the case of a −1 V ground shift, to 2.0-2.4 V for a +1 V ground shift. Therefore, the LVDS input buffer has an input operating range from 0.0-2.4 V.
Since many differential I/O standards, including LVDS, are commonly used in digital systems, it is advantageous if an input buffer circuit is compatible with and able to support multiple differential I/O standards. In particular, it is often desirable for the input buffer circuit of an LVDS receiver to be able to properly receive and process signals formatted according to other differential I/O standards. However, for some other differential I/O standards, such as the CML (current mode logic) and PCML (pseudo current mode logic) standards, the input operating range is designed to be at or near the VCC voltage level. For example, in the CML standard, the input voltage may swing from 0.6 V below VCC to VCC. Where VCC=3.3. V, the CML input operating range is from 2.7-3.3 V. Unfortunately, however, the differential amplifier circuitry in existing LVDS input buffer circuits generally does not respond well to input voltages that are higher than 2.4 V and therefore outside the LVDS operating range.
Consequently, there is a need for an input buffer circuit that is compatible with differential input signals for different digital I/O standards, even when the input voltage operating ranges for the different standards vary. In addition, there is a more specific need for an input buffer circuit that fully supports both LVDS and other differential I/O standard signals such as CML and PCML signals. Furthermore, it would be especially desirable to provide an input buffer circuit, originally designed for one I/O standard, that is readily adapted to support other I/O signal standards while still using a significant part of the original input buffer circuitry.